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Re: CVS Update@-mips.org: linux

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: CVS Update@-mips.org: linux
From: Dominic Sweetman <dom@mips.com>
Date: Thu, 3 Apr 2003 17:31:44 +0100
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
In-reply-to: <Pine.GSO.3.96.1030403181029.19058I-100000@delta.ds2.pg.gda.pl>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20030403174219.A4276@linux-mips.org> <Pine.GSO.3.96.1030403181029.19058I-100000@delta.ds2.pg.gda.pl>
Sender: linux-mips-bounce@linux-mips.org
Maciej W. Rozycki (macro@ds2.pg.gda.pl) writes:

> Hmm, that's even more interesting -- how can instruction fetches be
> distinguished from data reads externally???

The length of the burst is encoded in the bus command sent out by the
R4000 at the beginning of a read or write cycle.  For the system to
work, the memory controller has to be able to do the right thing for
both of the lengths which might happen...

It's very hard to see how a system could fail to work by making the
I-cache line the same size as a D-cache line.

> Then again, the memory controller shouldn't be able to observe
> inter-cache data moves.

This is true: for L2-equipped chips I assume you can't see the
difference between I- and D-.

--
Dominic
MIPS Technologies UK.


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