| To: | Pete Popov <ppopov@mvista.com> |
|---|---|
| Subject: | Re: Au1500 hardware cache coherency |
| From: | "Maciej W. Rozycki" <macro@ds2.pg.gda.pl> |
| Date: | Wed, 2 Apr 2003 14:17:14 +0200 (MET DST) |
| Cc: | Hartvig Ekner <hartvig@ekner.info>, Pete@ekner.info, Popov@ekner.info, Linux MIPS mailing list <linux-mips@linux-mips.org> |
| In-reply-to: | <1049221364.26674.248.camel@zeus.mvista.com> |
| Organization: | Technical University of Gdansk |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| Sender: | linux-mips-bounce@linux-mips.org |
On 1 Apr 2003, Pete Popov wrote: > > I'm not quite sure whether ld_mmu_mips32 is called after au1x00 setup, but > > if it is, > > the bit is cleared, never to be set again. Maybe the c0_config macroes > > should be changed > > due to errata #4? > > I doubt Ralf is going to change common macros to fix a specific bug. You'd better ask instead of guessing. I would see no problem with such a workaround IF done cleanly. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + |
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