There are data cache snoop bugs with respect to PCI on the Au1500. For the
Au1500s soldered on DbAu1500 boards to-date, PCI can not use coherent
transactions. Details in the Specification Update for the Au1500
-> Technical Resources
-> AMD Alchemy Solutions Development Board Support
Login with your board and you'll be presented with various docs,
Hartvig Ekner wrote:
I am attempting to use the HW coherency feature of the AU1500 to avoid SW
flushes and increase the performance.
In the config-shared.in file, I can see that the CONFIG_NONCOHERENT_IO define
is always set for the AMD
eval boards, which results in SW cache flushes when dma_cache_xxx functions are
called. If HW coherency is
working, this define should not be set.
However, in your drivers, you only call the dma_cache functions from
au1000/common/usbdev.c, but not from e.g. the ethernet
driver or the audio driver. Is this intentional? It seems that the ethernet &
audio driver already relies on HW
coherency to function correctly (and it also sets the MAC enable bits
accordingly, to force all ETH DMA
accesses to be coherent), so why not USB also?
When turning off NONCOHERENT_IO, there are some bugs (not in AU1000 code) which
prevents the code from
compiling, but I have fixed these. And the kernel boots, but during some large
disk-copy tests, I get occasional
data errors which I'm looking in to.
So before spending more time on debugging this, and creating patches for using
HW coherency, I wanted to hear
your input - maybe there are known problems in the Au1500 coherency