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Re: Disabling lwl and lwr instruction generation

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Disabling lwl and lwr instruction generation
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
Date: 14 Mar 2003 00:21:03 +0000
Cc: Ranjan Parthasarathy <ranjanp@efi.com>, Richard Hodges <rh@matriplex.com>, linux-mips@linux-mips.org
In-reply-to: <20030313223529.D30512@linux-mips.org>
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On Thu, 2003-03-13 at 21:35, Ralf Baechle wrote:
> Replace those unaligned copies with a word-wise or even bytewise copying.
> Not good for performance but ...

Depends on (src^dest) & 3. Glibc may have the code you need to get it
right, although it will also depend on how smart the cpu cache is - if
you have a write through cache then shift/mask/write in 32/64 chunks
may be fastest


Alan

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