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Re: Disabling lwl and lwr instruction generation

To: Ranjan Parthasarathy <ranjanp@efi.com>
Subject: Re: Disabling lwl and lwr instruction generation
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 13 Mar 2003 22:35:29 +0100
Cc: Richard Hodges <rh@matriplex.com>, linux-mips@linux-mips.org
In-reply-to: <D9F6B9DABA4CAE4B92850252C52383AB07968241@ex-eng-corp.efi.com>; from ranjanp@efi.com on Thu, Mar 13, 2003 at 10:09:03AM -0800
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On Thu, Mar 13, 2003 at 10:09:03AM -0800, Ranjan Parthasarathy wrote:

> From the gcc sources, the compiler generates the lwl,lwr etc. in the block
> move code in gcc/config/mips/mips.c ( output_block_move ). 
> 
> There is an option -mmemcpy which tells gcc to use a memcpy compiled in
> with the sources for this block move instead of gcc genetrating code. The
> problem however with this is that arch/mips/lib/memcpy.S is optimized
> using lwl,lwr,swl,swr. If this can be  modified so that lwl,lwr,swl,swr
> is used if enabled as a kernel option, it might work very well. 

Replace those unaligned copies with a word-wise or even bytewise copying.
Not good for performance but ...

  Ralf

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