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RE: Disabling lwl and lwr instruction generation

To: "Ralf Baechle" <ralf@linux-mips.org>, "Richard Hodges" <rh@matriplex.com>
Subject: RE: Disabling lwl and lwr instruction generation
From: "Ranjan Parthasarathy" <ranjanp@efi.com>
Date: Thu, 13 Mar 2003 10:00:47 -0800
Cc: <linux-mips@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
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Thread-topic: Disabling lwl and lwr instruction generation
Thanks for all your replies and no I am not working on the chinese processor 
:-). BTW it would be nice to have a mips option on override cpu options for 
disabling the lwl,lwr,swl,swr similar to "Cpu has ll/sc".

Thanks

Ranjan

-----Original Message-----
From: Ralf Baechle [mailto:ralf@linux-mips.org]
Sent: Wednesday, March 12, 2003 5:34 PM
To: Richard Hodges
Cc: Ranjan Parthasarathy; 'linux-mips@linux-mips.org'
Subject: Re: Disabling lwl and lwr instruction generation


On Wed, Mar 12, 2003 at 04:50:53PM -0800, Richard Hodges wrote:

> I got lwl and lwr from a memcpy() with two void pointers...
> 
> I quickly changed those to the (aligned) structure pointers instead, and
> then memcpy() changed to ordinary word loads and stores.
> 
> So, is somebody starting a toolchain for that new Chinese CPU? :-)

Wouldn't be the first processor without lwl/lwr instructions.  There have
been a few that didn't implement it for silly bean^Wgate counting issues
others have done it for patent and licensing reasons.

(Afair MIPS's patent is about to expire and IBM's prior art patent in the
same area is even way older but that legalese ...)

  Ralf

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