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Re: Disabling lwl and lwr instruction generation

To: Richard Hodges <rh@matriplex.com>
Subject: Re: Disabling lwl and lwr instruction generation
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 13 Mar 2003 02:33:45 +0100
Cc: Ranjan Parthasarathy <ranjanp@efi.com>, "'linux-mips@linux-mips.org'" <linux-mips@linux-mips.org>
In-reply-to: <Pine.BSF.4.50.0303121647400.95890-100000@mail.matriplex.com>; from rh@matriplex.com on Wed, Mar 12, 2003 at 04:50:53PM -0800
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On Wed, Mar 12, 2003 at 04:50:53PM -0800, Richard Hodges wrote:

> I got lwl and lwr from a memcpy() with two void pointers...
> 
> I quickly changed those to the (aligned) structure pointers instead, and
> then memcpy() changed to ordinary word loads and stores.
> 
> So, is somebody starting a toolchain for that new Chinese CPU? :-)

Wouldn't be the first processor without lwl/lwr instructions.  There have
been a few that didn't implement it for silly bean^Wgate counting issues
others have done it for patent and licensing reasons.

(Afair MIPS's patent is about to expire and IBM's prior art patent in the
same area is even way older but that legalese ...)

  Ralf

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