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Re: [patch] Cobalt IRQ handler CP0 interlock?

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [patch] Cobalt IRQ handler CP0 interlock?
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Fri, 21 Feb 2003 13:11:58 +0100 (MET)
Cc: linux-mips@linux-mips.org
In-reply-to: <20030220195314.C30853@linux-mips.org>
Organization: Technical University of Gdansk
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
On Thu, 20 Feb 2003, Ralf Baechle wrote:

> >  Does Cobalt have a processor that implements its pipeline differently or
> > interlocks on CP0 loads?  If not, I'll apply the following fix. 
> 
> Mfc0 doesn't need a nops on any R4000 class CPU I know of.

 Well, my MIPS R4k manual is vague on this matter and my IDT software
manual for R3k, R4k, R5k is even explicit on the load delay slot of mfc0. 
But a run-time test proves otherwise. 

 I stand corrected then unless someone finds a counter-example.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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