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Re: [RFC & PATCH] fixing tlb flush race problem on smp

To: jsun@mvista.com
Subject: Re: [RFC & PATCH] fixing tlb flush race problem on smp
From: Atsushi Nemoto <anemo@mba.sphere.ne.jp>
Date: Fri, 14 Feb 2003 13:48:25 +0900 (JST)
Cc: ralf@linux-mips.org, quintela@mandrakesoft.com, linux-mips@linux-mips.org, nemoto@toshiba-tops.co.jp
In-reply-to: <20030204160250.F5149@mvista.com>
Organization: TOSHIBA Personal Computer System Corporation
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20030127170346.S11633@mvista.com> <20030129090627.D7741@linux-mips.org> <20030204160250.F5149@mvista.com>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Tue, 4 Feb 2003 16:02:50 -0800, Jun Sun <jsun@mvista.com> said:
jsun> Here is a complete patch for both mips/mips64, 2.4 and 2.5.  Of
jsun> course only 2.4/mips combo is tested.

The attached patch seems to break r3k codes.  Here is a patch to fix
it (only for 2.4/mips).

diff -ur linux-mips-cvs/include/asm-mips/mmu_context.h 
linux.new/include/asm-mips/mmu_context.h
--- linux-mips-cvs/include/asm-mips/mmu_context.h       Fri Feb 14 09:41:31 2003
+++ linux.new/include/asm-mips/mmu_context.h    Fri Feb 14 13:40:24 2003
@@ -151,7 +151,7 @@
 
        if (test_bit(cpu, &mm->cpu_vm_mask))  {
                get_new_mmu_context(mm, cpu);
-               write_c0_entryhi(cpu_context(cpu, mm) & 0xff);
+               write_c0_entryhi(cpu_context(cpu, mm) & ASID_MASK);
        } else {
                /* will get a new context next time */
                cpu_context(cpu, mm) = 0;
---
Atsushi Nemoto

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