linux-mips
[Top] [All Lists]

Re: unaligned load in branch delay slot

To: Brad Parker <brad@parker.boston.ma.us>
Subject: Re: unaligned load in branch delay slot
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 29 Jan 2003 07:40:10 +0100
Cc: Geert Uytterhoeven <geert@linux-m68k.org>, Mike Uhler <uhler@mips.com>, Linux/MIPS Development <linux-mips@linux-mips.org>
In-reply-to: <200301290139.h0T1d3R01891@p2.parker.boston.ma.us>; from brad@parker.boston.ma.us on Tue, Jan 28, 2003 at 08:39:03PM -0500
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <geert@linux-m68k.org> <200301290139.h0T1d3R01891@p2.parker.boston.ma.us>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.2.5.1i
On Tue, Jan 28, 2003 at 08:39:03PM -0500, Brad Parker wrote:

> I had a problem in tcp_rcv_established() where this "if" would trigger
> even though "th->syn" was zero:
> 
> ...
>       if (th->syn && !before(TCP_SKB_CB(skb)->seq, tp->rcv_nxt)) {
> ...
> 
> It turned out the tcp header was 'misaligned' after coming across a
> usb link.  I never figured out why it was failing, but it was clearly
> the emulation code which was doing the wrong thing.  This was on an
> alchemy au1000 (MIPS32).

A few days ago I fixed a special case in cvs where the unaligned handler
was misshandling the special case where

        bxx     $r1, dest
        load    $r1, offset($r2)

both instruction are using the same register $r1 and the effective address
offset + $r2 was missaligned.  In that case the emulation code was
executing the load instruction first then using the loaded value to deciede
if the branch was taken.

I know the bug was hitting in the netfilter code but chances are there are
other places in the network code affected as well.

  Ralf

<Prev in Thread] Current Thread [Next in Thread>