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Possible bug in gcc for mips?

To: linux-mips@linux-mips.org
Subject: Possible bug in gcc for mips?
From: Long Li <long21st@yahoo.com>
Date: Tue, 28 Jan 2003 19:14:21 -0800 (PST)
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hi,

I built a gcc 3.0.4 mips crosscompiler on redhat
7.1(binutils 2.11.2). I embedded some inline assembly
in the C code. This is what I did:

 //get SR Bit from Status Register
 register unsigned int status_reg;
 register unsigned int warm_reset, cold_reset;

 asm volatile ("mfc0 %0,$12" :: "r"(status_reg));

  if ((status_reg >> 20) & 0x1) {
        warm_reset++;
  }
  else {
     cold_reset++;
  }


I compiled and disassembly the output. This is what
shows in the disassembly:

00000000 <init>:
   0:   27bdfff0        addiu   sp,sp,-16
   4:   afbe0008        sw      s8,8(sp)
   8:   03a0f025        move    s8,sp
   c:   8fc20004        lw      v0,4(s8)
  10:   40026000        mfc0    v0,t4
  14:   8fc30004        lw      v1,4(s8)
  18:   00000000        nop
  1c:   00031502        srl     v0,v1,0x14
  20:   30420001        andi    v0,v0,0x1
  24:   10400009        beqz    v0,4c <init+0x4c>
  28:   00000000        nop

You can see the condition depends on the value of v1,
which is loaded from the stack, instead of v0, which
is the expected status register.

Is this a possible bug or a feature for gcc 3.0.4?


Thanks a lot!


Long


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