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[OT] Re: unaligned load in branch delay slot

Subject: [OT] Re: unaligned load in branch delay slot
Date: 28 Jan 2003 16:30:09 -0500
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Original-recipient: rfc822;
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Source-info: Sender is really
On Tue, 2003-01-28 at 14:48, Mike Uhler wrote:

> If the patch assumes that one can look backward by one instruction
> in the STATIC code to determine if the instruction is in a
> delay slot, one can not have code that jumps directly to the
> instruction following another branch, as this would cause the
> code to assume that it was in the delay slot of the branch.

A while back, when working on a different architecture that also had
branch delay slots, it took me a while to get my head around the
branch-in-a-delay-slot case, e.g.

10:  b 100
20:  b 30
30:  foo
100: bar

where the actual program flow would be


and instruction 100 would be considered to be in the delay slot of 20.

I was *very* happy when I first looked at MIPS to see that this was 
specified as unpredictable, even if it was pretty cool to be able to
make the CPU execute a single instruction in the middle of nowhere. 
Pointless, but cool.  :)


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