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Re: unaligned load in branch delay slot

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: unaligned load in branch delay slot
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 28 Jan 2003 13:54:53 +0100
Cc: Geert Uytterhoeven <geert@linux-m68k.org>, Mike Uhler <uhler@mips.com>, Linux/MIPS Development <linux-mips@linux-mips.org>
In-reply-to: <Pine.GSO.3.96.1030128130651.22934A-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Tue, Jan 28, 2003 at 01:30:03PM +0100
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References: <20030128124750.A25956@linux-mips.org> <Pine.GSO.3.96.1030128130651.22934A-100000@delta.ds2.pg.gda.pl>
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On Tue, Jan 28, 2003 at 01:30:03PM +0100, Maciej W. Rozycki wrote:

>  Actually I have a datasheet for the Vr4121 (which is a Vr4120 plus some
> glue logic for specific peripherals) and it explicitly states whenever
> cp0.EPC points to a preceding branch/jump of a faulting instruction, the
> cp0.Cause.BD bit is set.  Maybe there is an errata sheet available.

Honestly I'd not expect this to be documented in a NEC manual - they
basically look like the description of the processor core is the same for
basically all the Vr4xxx processors and SOCs.

>  Additionally the processor is "nice" enough to implement the MIPS III ISA
> (with the MIPS16 extension) except ll/sc, lld/scd, sigh...  So the
> emulation would need to be ported to the 64-bit kernel if we were to
> support this processor in the 64-bit mode. 

Maximum agreement on the "sigh" part ...

  Ralf

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