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Re: unaligned load in branch delay slot

To: Geert Uytterhoeven <geert@linux-m68k.org>
Subject: Re: unaligned load in branch delay slot
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 28 Jan 2003 12:47:50 +0100
Cc: Mike Uhler <uhler@mips.com>, Linux/MIPS Development <linux-mips@linux-mips.org>
In-reply-to: <Pine.GSO.4.21.0301281024060.9269-100000@vervain.sonytel.be>; from geert@linux-m68k.org on Tue, Jan 28, 2003 at 10:30:20AM +0100
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On Tue, Jan 28, 2003 at 10:30:20AM +0100, Geert Uytterhoeven wrote:

> If it happens, I should get a SIGILL, right?

Right.

Hmm...  If you can't reproduce this anymore I guess we should pull this
patch again?  Despite Mike basically acknowledging that such behaviour
exists I don't feel to well about applying patches for non-reproducable
processor behaviour and would rather prefer to wait until we believe to
know the full details.

?

> > +   set_fs(seg);
> 
> `seg' is never initialized?

Yep ...

> > +   case bcond_op:
> > +   case j_op:
> > +   case jal_op:
> > +   case beq_op:
> > +   case bne_op:
> > +   case blez_op:
> > +   case bgtz_op:
> > +   case beql_op:
> > +   case bnel_op:
> > +   case blezl_op:
> > +   case bgtzl_op:
> > +   case jalx_op:
> > +           return 1;       
> 
> I think you can remove the unconditional jumps, cfr. Mike's comments.

That's one of the points where I felt a bit unsafe about the extend of
the issue so I left the jumps in.  Anyway, why should it make a difference
if an instruction is conditional or not?

> Isn't the Vr4120A core MIPS32?

Vr4120 is MIPS III.

  Ralf

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