| To: | Adam Kiepul <Adam_Kiepul@pmc-sierra.com> |
|---|---|
| Subject: | Re: A question on Linux SMP and cache coherency |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Fri, 24 Jan 2003 15:31:31 +0100 |
| Cc: | "'linux-mips@linux-mips.org'" <linux-mips@linux-mips.org> |
| In-reply-to: | <71690137A786F7428FF9670D47CB95ED10DF6F@SJE4EXM01>; from Adam_Kiepul@pmc-sierra.com on Thu, Jan 23, 2003 at 03:17:25PM -0800 |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <71690137A786F7428FF9670D47CB95ED10DF6F@SJE4EXM01> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.2.5.1i |
On Thu, Jan 23, 2003 at 03:17:25PM -0800, Adam Kiepul wrote: > I would really appreciate if anyone could tell me whether > Hardware-maintained cache coherency between processors is required for > Linux SMP operation. (Sending just one copy of a posting is sufficient ...) There have been imho fairly ridiculous attempts at constructing dual-core SMPs for the use with Linux/MIPS by changing the kernel to 16kB page size [1] and using write through-caches plus some extra hacks. Needless to say the solution is about as stupid as something can be and is probably going to perform worse than a uniprocessor ... Ralf [1] good idea for other reasons but completly stupid in this context |
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