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Re: A question on Linux SMP and cache coherency

To: Adam Kiepul <Adam_Kiepul@pmc-sierra.com>
Subject: Re: A question on Linux SMP and cache coherency
From: Keith Owens <kaos@sgi.com>
Date: Fri, 24 Jan 2003 10:32:31 +1100
Cc: "'linux-mips@linux-mips.org'" <linux-mips@linux-mips.org>
In-reply-to: Your message of "Thu, 23 Jan 2003 15:21:01 -0800." <71690137A786F7428FF9670D47CB95ED10DF71@SJE4EXM01>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
On Thu, 23 Jan 2003 15:21:01 -0800, 
Adam Kiepul <Adam_Kiepul@pmc-sierra.com> wrote:
>       I would really appreciate if anyone could tell me whether 
> Hardware-maintained cache coherency between processors is required for Linux 
> SMP operation.

http://www.uwsg.iu.edu/hypermail/linux/kernel/0007.3/1220.html


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