On Thu, Dec 12, 2002 at 12:52:42PM +0000, Dominic Sweetman wrote:
> > Flushes are very expensive operations, on the order of 16 cycles per
> > cacheline plus memory delay.
> Hmm. Not on most MIPS CPUs; the internal cost of running the
> writeback cache-op instructions is typically around 3 clocks per
> cache-line. But this is misleading anyway... too CPU-centric.
Most MIPS manuals unfortunately do not document the execution time of
cache instructions at all. This thread is specific to the SGI IP32 aka
O2 which comes with three processor options, the r5000, the R10000 and
the R12000; the R5000's timing should not be too far off from the R4600.
So you got me to dig out my super dusty R4600/R4700 manual ... Hit_-
Writeback_D costs 7 cycles for a miss, 12 for a hit if the line is clean
and 14 if the line is dirty. Add another 3 cycles if the store or response
buffers are busy, add even more if the writeback buffer was filled up.
> The associated memory operations are the slowest thing about cacheops,
> always. Memory accesses (120ns is good) are much, much slower than an
> instruction time on a modern CPU (1-5ns).
> So for your framebuffer, it's the write which does for you. If you
> use uncached mode and write 32-bit words that's 120ns/word. You can
> get a cacheline-sized burst of 8 words in and out in roughly the same
> amount of time.
Forgot the numbers but SGI's IP32 memory subsystem is rather fast even
though it's fairly old.