Ralf Baechle (firstname.lastname@example.org) writes:
> Flushes are very expensive operations, on the order of 16 cycles per
> cacheline plus memory delay.
Hmm. Not on most MIPS CPUs; the internal cost of running the
writeback cache-op instructions is typically around 3 clocks per
cache-line. But this is misleading anyway... too CPU-centric.
The associated memory operations are the slowest thing about cacheops,
always. Memory accesses (120ns is good) are much, much slower than an
instruction time on a modern CPU (1-5ns).
So for your framebuffer, it's the write which does for you. If you
use uncached mode and write 32-bit words that's 120ns/word. You can
get a cacheline-sized burst of 8 words in and out in roughly the same
amount of time.
In most cases this means that cacheing the framebuffer and then
pushing it out will save a whole lot of time.
It's not absolutely certain: in most MIPS CPUs (write allocate as well
as writeback) you also pay to read in the framebuffer data. And it
tends to displace all sorts of other useful data from the cache, and
then you have to pay to bring it back again.
But in general the memory operations associated with write-backs and
invalidates are much more costly than the cacheops themselves.
MIPS Technologies (UK)
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone: +44 1223 706205 / fax: +44 1223 706250 / swbrd: +44 1223 706200