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Re: possible Malta 4Kc cache problem ...

To: Carsten Langgaard <carstenl@mips.com>
Subject: Re: possible Malta 4Kc cache problem ...
From: Jun Sun <jsun@mvista.com>
Date: Wed, 4 Dec 2002 14:19:00 -0800
Cc: "Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org, jsun@mvista.com
In-reply-to: <3DEDD414.3854664F@mips.com>; from carstenl@mips.com on Wed, Dec 04, 2002 at 11:08:20AM +0100
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References: <20021203224504.B13437@mvista.com> <007501c29b78$f34680e0$10eca8c0@grendel> <3DEDD414.3854664F@mips.com>
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On Wed, Dec 04, 2002 at 11:08:20AM +0100, Carsten Langgaard wrote:
> I have just tried your test on a 4Kc and I see no problems.
> However I'm running on our internal kernel sources, and as Kevin mention we 
> have
> changed a fixed a few things in this area.
> As Kevin also mention it sure look more like a I-cache invalidation problem,
> rather than a D-cache flush problem, as the 4Kc has a write-through cache.
> One think you could try, is our latest kernel release. You can find it here:
> ftp://ftp.mips.com/pub/linux/mips/kernel/2.4/images/
>

Yes, the problem still exists with this kernel.

Try to move the source tree to /root/, rename top dir to "try18", 
re-make the binary, and try again.

This problem is tricky to reproduce.  The location of the tree
definitely matters.  I am testing 32bit LE version.  Have not
tried BE.

I think I have pinned down the problem.  See my other follow-up posting.

Jun

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