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Re: watch exception only for kseg0 addresses..?

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: watch exception only for kseg0 addresses..?
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Mon, 25 Nov 2002 16:47:33 +0100 (MET)
Cc: Daniel Jacobowitz <dan@debian.org>, atul srivastava <atulsrivastava9@rediffmail.com>, linux-mips@linux-mips.org
In-reply-to: <20021125160800.A22590@linux-mips.org>
Organization: Technical University of Gdansk
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
On Mon, 25 Nov 2002, Ralf Baechle wrote:

> MIPS64 extends that to also support instruction address matches; the
> granularity can be set anywhere from 8 bytes to 4kB; in addition ASID
> matching and a global bit can be used for matching.  A MIPS64 CPU can
> support anywhere from 0 to 4 such watch registers.

 Actually up to eight -- for all dmfc0/dmtc0 3-bit "sel" values, if I read
it correctly.

> The global bit stuff would only be useful for in-kernel use, I think.  The
> ASID thing could be used to implement watchpoints for an entire process, not
> just per thread though I doubt there is much use for something like that.

 Well, there are two options only -- either use global matching or ASID
matching.  What else would you expect?  Do you mean lazy vs immediate
switching? 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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