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Re: Once again: test_and_set for CPUs w/o LL/SC

To: "Kevin D. Kissell" <kevink@mips.com>
Subject: Re: Once again: test_and_set for CPUs w/o LL/SC
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Tue, 15 Oct 2002 17:17:24 +0200 (MET DST)
Cc: Johannes Stezenbach <js@convergence.de>, linux-mips@linux-mips.org
In-reply-to: <01fd01c26e1d$add77240$10eca8c0@grendel>
Organization: Technical University of Gdansk
Original-recipient: rfc822;linux-mips@linux-mips.org
Reply-to: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Sender: linux-mips-bounce@linux-mips.org
On Mon, 7 Oct 2002, Kevin D. Kissell wrote:

> That's probably going to be a more reliable design,
> though I would still consider leaving the TLB refill handler
> untouched and counting on the fact that k1 must contain
> a non-lethal EntryLo value on return from the exception.

 Well, there is a "nop" just before the "eret" in all R4k-style TLB
exception handlers.  I see no problem to use the slot for explicit
clobbering of k0 or k1 with a single instruction like "li" or "lui". 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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