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Re: Promblem with PREF (prefetching) in memcpy

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Promblem with PREF (prefetching) in memcpy
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Fri, 4 Oct 2002 15:32:29 +0200 (MET DST)
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>, Carsten Langgaard <carstenl@mips.com>, Dominic Sweetman <dom@algor.co.uk>, linux-mips@linux-mips.org
In-reply-to: <20021004151718.A16064@linux-mips.org>
Organization: Technical University of Gdansk
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
On Fri, 4 Oct 2002, Ralf Baechle wrote:

> >  For MIPS a bus error exception is not an address related exception by
> > definition (not surprising, anyway).  Specifically, the BadVaddr register
> > is not set upon one.
> 
> A particular pain is the exception can be delayed almost arbitrarily due to
> posted writes.  So quite frequently there is no easy association between
> the machine state at exception time and the cause ...

 Hmm, I'm not sure if it's permitted to signal a bus exception for
asynchronous write cycles.  At least the R3k and the R4000/R4400
specifications explictly forbid them and state that a general interrupt
has to be used in such a case instead (and at least the DECstations get
this circuitry right -- all of them have a dedicated gp interrupt input
for bus errors on a write).  Later chips might have relaxed this
requirement though -- I don't know at the moment.

 Anyway, the address which is involved in the cycle resulting in a bus
exception is always valid and the reason lies elsewhere -- e.g. it may be
a bus timeout or a data ECC error. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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