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Re: Promblem with PREF (prefetching) in memcpy

To: Carsten Langgaard <carstenl@mips.com>
Subject: Re: Promblem with PREF (prefetching) in memcpy
From: "Dr. David Alan Gilbert" <gilbertd@treblig.org>
Date: Fri, 4 Oct 2002 13:35:54 +0100
Cc: Dominic Sweetman <dom@algor.co.uk>, Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
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* Carsten Langgaard (carstenl@mips.com) wrote:

> > For a Linux user program, at least, memory pages are "memory-like":
> > reads are guaranteed to be side-effect free, so any outlying
> > prefetches are harmless.  It's hard to see any circumstance where an
> > accessible cacheable location would lead to bad side-effects on read.
> 
> What about an UART RX register, we might loose a character ?
> You can also configure you system, so you get a external interrupt from you
> system controller in case of a bus error, there is no way the CPU can
> relate this interrupt to the prefetching.

Well those woudn't be cacheable (hmm what happens to a prefetch on none
cached areas?) and also you could argue that you shouldn't be proding
UARTs from user space (although you could equally argue that it is
perfectly valid - but if you were doing it you probably wouldn't
be attacking them with a memcpy).

Dave
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