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Re: Interrupt handling....

To: Dominic Sweetman <dom@algor.co.uk>
Subject: Re: Interrupt handling....
From: Matthew Dharm <mdharm@momenco.com>
Date: Wed, 4 Sep 2002 09:40:14 -0700
Cc: Jun Sun <jsun@mvista.com>, Linux-MIPS <linux-mips@linux-mips.org>
In-reply-to: <200209040953.KAA17466@mudchute.algor.co.uk>; from dom@algor.co.uk on Wed, Sep 04, 2002 at 10:53:55AM +0100
Organization: Momentum Computer, Inc.
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References: <3D6E87EB.4010000@mvista.com> <NEBBLJGMNKKEEMNLHGAIEEMBCIAA.mdharm@momenco.com> <200209040953.KAA17466@mudchute.algor.co.uk>
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On Wed, Sep 04, 2002 at 10:53:55AM +0100, Dominic Sweetman wrote:
> 
> Matthew,
> 
> > Okay... I think I've got a problem that isn't covered by the usual
> > examples.
> 
> Possibly this is too simple an answer and is stuff you know quite well
> already...

Yeah, it is. See my response to Maciej's posting....

> > Which, as you can see, attempts to access address 0xfc00000c.
> 
> But that address is in the MIPS CPU's 'kseg2' region.  Addresses there
> are always translated by the TLB, and you haven't got an entry.

It's also the physical address.

And this is the heart of the problem.  I set up an ioremap, so I thought
that the TLB exception handler would fix this for me.  It looks like that
code won't do anything if the exception was generated from an interrupt...
Or am I reading it wrong?  I'm not an expert on the TLB code...

> You could read the book ("See MIPS Run")...

I read it quite some time ago.  My copy got very dog-eared before I had the
majority of the information committed to memory.  Nice book, BTW.

Matt

-- 
Matthew Dharm                              Work: mdharm@momenco.com
Senior Software Designer, Momentum Computer


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