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Re: [PATCH] Bring back R4600 V1.7 support

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: [PATCH] Bring back R4600 V1.7 support
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 20 Aug 2002 16:03:11 +0200
Cc: Jan-Benedict Glaw <jbglaw@lug-owl.de>, SGI MIPS list <linux-mips@oss.sgi.com>
In-reply-to: <Pine.GSO.3.96.1020820153410.8700F-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Tue, Aug 20, 2002 at 03:55:34PM +0200
References: <Pine.GSO.3.96.1020820152046.8700E-100000@delta.ds2.pg.gda.pl> <Pine.GSO.3.96.1020820153410.8700F-100000@delta.ds2.pg.gda.pl>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5.1i
On Tue, Aug 20, 2002 at 03:55:34PM +0200, Maciej W. Rozycki wrote:

>  An additional thought that just came to my mind: it might be possible to
> avoid masking interrupts with a dummy ll/sc pair only checking if an
> interrupt happened within the critical code.  It should be easy to
> validate since only a single mask of a processor would make use of the
> code.  The real question is: "Do the affected cache operations corrupt any
> state or do they only work on wrong lines?"  If the latter, the approach
> should work for all operations except from "Hit_Invalidate_D" that
> corrupts state by definition (but it isn't used by any R4k processor, so
> it may simply be replaced with a panic()).  Unfortunately, the knowledge
> does no longer exist within IDT, but maybe someone else knows? 

I was thinking about that already but the erratas don't provide enough
details.  The only problem I can see is that ll/sc are fairly slow on some
architectures.  They're supposed to be quite light according to the docs
but in reality I benchmarked ~ 13 cycles for a spinlock on a R10000 and
~ 44 on a more recent chip.

  Ralf


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