| To: | Carsten Langgaard <carstenl@mips.com> |
|---|---|
| Subject: | Re: [update] [patch] linux: Cache coherency fixes |
| From: | "Maciej W. Rozycki" <macro@ds2.pg.gda.pl> |
| Date: | Fri, 2 Aug 2002 10:36:57 +0200 (MET DST) |
| Cc: | Ralf Baechle <ralf@oss.sgi.com>, linux-mips@fnet.fr, linux-mips@oss.sgi.com |
| In-reply-to: | <3D4A4191.DF5EFFC4@mips.com> |
| Organization: | Technical University of Gdansk |
| Sender: | owner-linux-mips@oss.sgi.com |
On Fri, 2 Aug 2002, Carsten Langgaard wrote: > The Malta board is a system that both run coherent and non-coherent, so I > would > prefer, that we either make the coherency a configuration option or make it > possible to determine at run time. The latter, definitely. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + |
| Previous by Date: | Re: [update] [patch] linux: Cache coherency fixes, Carsten Langgaard |
|---|---|
| Next by Date: | Re: [patch] MIPS64 R4k TLB refill CP0 hazards, Carsten Langgaard |
| Previous by Thread: | Re: [update] [patch] linux: Cache coherency fixes, Carsten Langgaard |
| Next by Thread: | Re: [update] [patch] linux: Cache coherency fixes, Ralf Baechle |
| Indexes: | [Date] [Thread] [Top] [All Lists] |