| To: | "Maciej W. Rozycki" <macro@ds2.pg.gda.pl> |
|---|---|
| Subject: | Re: [patch] MIPS64 R4k TLB refill CP0 hazards |
| From: | Ralf Baechle <ralf@oss.sgi.com> |
| Date: | Wed, 31 Jul 2002 22:31:58 +0200 |
| Cc: | Carsten Langgaard <carstenl@mips.com>, linux-mips@fnet.fr, linux-mips@oss.sgi.com |
| In-reply-to: | <Pine.GSO.3.96.1020731133006.10088A-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Wed, Jul 31, 2002 at 01:34:17PM +0200 |
| References: | <20020731004702.A2142@dea.linux-mips.net> <Pine.GSO.3.96.1020731133006.10088A-100000@delta.ds2.pg.gda.pl> |
| Sender: | owner-linux-mips@oss.sgi.com |
| User-agent: | Mutt/1.2.5.1i |
On Wed, Jul 31, 2002 at 01:34:17PM +0200, Maciej W. Rozycki wrote: > > Nope, on R4000 four cycles are needed between the tlbwr and a eret > > instruction; on the R4600 just two. > > Ugh, I missed this entirely, thanks for pointing it out. The doc implies > three cycles for the R4000 actually, though. I doublechecked the docs for the R4700 as well - just one cycle needed between a tlbw and eret. Ralf |
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