Re: [patch] MIPS64 R4k TLB refill CP0 hazards

["Maciej W. Rozycki" <macro@ds2.pg.gda.pl>]

On Wed, 31 Jul 2002, Ralf Baechle wrote:

> Nope, on R4000 four cycles are needed between the tlbwr and a eret
> instruction; on the R4600 just two.

 Ugh, I missed this entirely, thanks for pointing it out.  The doc implies
three cycles for the R4000 actually, though. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
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