Re: [patch] MIPS64 R4k TLB refill CP0 hazards

[Ralf Baechle <ralf@oss.sgi.com>]

On Tue, Jul 30, 2002 at 02:44:32PM +0200, Maciej W. Rozycki wrote:

>  Since the handler is critical for performance, it would be desireable to
> have separate versions tuned for particular CPUs.  The branch for the
> R4400 seems appropriate as it works unlike the documented code: the
> R4000/R4400 manual as available from the MIPS site states a single
> intervening instruction is needed before the last move to EntryLo and a
> "tlbwr" or "tlbwi" (see Table F-1 and F-2).  So I conclude the branch is
> really a workaround for a kind of erratum or a specification change. 

Nope, on R4000 four cycles are needed between the tlbwr and a eret
instruction; on the R4600 just two.

  Ralf