"Maciej W. Rozycki" wrote:
> Well, it looks possible for a CPU with cache lines wider than 32-bits
> (are there any such R3k-class CPUs?), indeed.
Yes, IDT R3081 has 16-byte I-cacheline. It also may have 16-byte
D-cacheline, it depends on DB Refill set, may be set by wiring and in
software too. DB Refill is here to support burst reads modern DRAMs
> > Unfortunately, the behaviour depends on whether miss occurs, what
> > instructions are loaded, how they are aligned, and so on. It means, if
> > you get crash on this kernel version, you won't get a crash on another.
> > If you add debug routines, everything is OK. Other black magic tricks
> > are also here. (As you may guess, I explain my real experience here.
> > :-). Analyzer doesn't help, bus transactions look good.)
> How true -- I've seen such nastinesses, too. :-/ Except that I don't
> have an analyzer.
Don't care, it doesn't help in such situations.
> > In order to avoid this, CPU shall either perform the check again or
> > freeze everything on the cache swap operation. The latter doesn't look
> > real. Anyway, it's a lot of additional unnatural logic. So, the
> > requirement to run swapping operation uncached looks reasonable.
> Well, the simplest effective approach would be a third alternative, i.e.
> to make swapping happen only when no fill is in progress. Trivial logic
> with a single D latch on the swap signal should suffice -- I don't think
> the save on omitting it is worth breaking architecture specs and
In two words, it's unclear when there are no fills. Too much situations,
additional stall condition (which may break spec anyway). I can't
present full explanation, sorry. You have to believe. :-)
BTW, I reread my R3081 HW Manual and found two intresting places about
"These mechanisms [cache sizing, cache flushing] are enabled through the
use of the ⌠IsC■ (Isolate Cache) and SwC (Swap Cache) bits of the status
register, which resides in the on-chip System Control Co-Processor
(CP0). Instructions which immediately precede and succeed these
operations must not be cacheable, so that the actual swapping/isolation
of the cache does not disrupt operation."
Note precede instructions.
Then, on cache sizeing:
[Famous algorithm that we implement]
Note that this software should operate as uncached. Once this algorithm
is done, software should return the caches to their normal state by
performing either a complete cache flush or an invalidate of those cache
lines modified by the sizing algorithm."