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Re: mips32_flush_cache routine corrupts CP0_STATUS with gcc-2.96

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: mips32_flush_cache routine corrupts CP0_STATUS with gcc-2.96
From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Date: Fri, 12 Jul 2002 14:26:58 +0400
Cc: linux-mips@oss.sgi.com
Organization: NIISI RAN
References: <Pine.GSO.3.96.1020711173440.7876G-100000@delta.ds2.pg.gda.pl>
Sender: owner-linux-mips@oss.sgi.com
"Maciej W. Rozycki" wrote:
> 
> On Thu, 11 Jul 2002, Gleb O. Raiko wrote:
> 
> > Have to check the cacheline at given address again. D-cache may have the
> > valid bit set for the cacheline at the same address. Address means
> > location in a cache, not memory. Check at address requires one extra
> > tick as opposed to checking the bit.
> 
>  Well, you issue an instruction word read from the cache.  The answer is
> either a hit, providing a word at the data bus at the same time (so you
> can't get a hit from one cache and data from the other) or a miss with no
> valid data -- you have to stall in this case, waiting for a refill.  

Let it be miss and stall.

>Then
> when data from the main memory arrives, it is latched in the cache (it
> doesn't really matter, which one now -- if it's the wrong one, then
> another refill will happen next time the memory address is dereferenced)
> and provided to the CPU at the same time.

At this time, CPU continues the execution of previous stalled
instruction. CPU knows the stalled instruction is in I-cache, but,
unfortunately, caches have been swapped already. The same cacheline in
the D-cache was valid bit set. CPU get data instead of code.

Regards,
Gleb.


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