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RE: mips32_flush_cache routine corrupts CP0_STATUS with gcc-2.96

To: "Sedjai, Mohamed" <MSedjai@tee.toshiba.de>
Subject: RE: mips32_flush_cache routine corrupts CP0_STATUS with gcc-2.96
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: Fri, 12 Jul 2002 11:26:41 +0200 (MEST)
Cc: Jon Burgess <Jon_Burgess@eur.3com.com>, Ralf Baechle <ralf@oss.sgi.com>, "Gleb O. Raiko" <raiko@niisi.msk.ru>, Linux/MIPS Development <linux-mips@oss.sgi.com>, carstenl@mips.com
In-reply-to: <CEEE372345CE51438B0EC15F09ADE2710910F8@dus04a.tsb-eu.com>
Sender: owner-linux-mips@oss.sgi.com
On Fri, 12 Jul 2002, Sedjai, Mohamed wrote:
> If you run instruction cache flushing cached, then the cache will be dirty
> when the routine returns. At least the line(s) containing the routine itself ?
> Or am I missing something ?

Since the contents of the instruction cache are never changed (except by a
cache load), an instruction cache line can never become dirty.

Dirty cache lines and cache line write back are an exclusive privilege of write
back data caches.

Gr{oetje,eeting}s,

                                                Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                                            -- Linus Torvalds


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