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Re: mips32_flush_cache routine corrupts CP0_STATUS with gcc-2.96

To: Ralf Baechle <ralf@oss.sgi.com>
Subject: Re: mips32_flush_cache routine corrupts CP0_STATUS with gcc-2.96
From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Date: Thu, 11 Jul 2002 12:48:28 +0400
Cc: Jon Burgess <Jon_Burgess@eur.3com.com>, linux-mips@oss.sgi.com
Organization: NIISI RAN
References: <80256BF2.004ECBE6.00@notesmta.eur.3com.com> <20020711021554.A3207@dea.linux-mips.net>
Sender: owner-linux-mips@oss.sgi.com
Ralf Baechle wrote:
> 
> On Wed, Jul 10, 2002 at 03:16:21PM +0100, Jon Burgess wrote:
> 
> > This may be caused by the cache routines running from the a cached kseg0, it
> > looks like it can be fixed by making sure that the are always called via
> > KSEG1ADDR(fn) which looks like it could be done with a bit of fiddling of 
> > the
> > setup_cache_funcs code. I have included a patch below which starts this, 
> > but I
> > haven't caught all combinations of how the routines are called.
> 
> While that could be done it's not a good idea; running code in KSEG1 is
> very slow.
> 

Unfortunately, it's required by manuals for some processors. As I know,
IDT HW manuals clearly state cache flush routines must operate from
uncached code and must access uncached data only. Examples are R30x1 CPU
series.

Regards,
Gleb.


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