Alan Cox wrote:
This patch fixes a tx underflow error for 79c973 chip. It essentially delay
the transmission until the whole packet is received into the on-chip sdram.
The patch is already accepted by Marcelo for the 2.4 tree, I think.
Which slows the stuff down for people with real computers.
Contrary to what it might appear at first glance, it does not really.
While it delays the start of a transmission of the first packet, the delay
does not aggregate in a steam of data. The bottle neck is either in upper
layer (how fact upper layer generates packets) or in the link layer (when we
exceed the maximum bandwitch of the wire, in which case we always have plenty
of full packets to send).
The delay itself is small (should be < 100us typically). So there is no
impact on interactive packets. Note if the delay is not small (e.g., on
system where PCI bus arbitration may be broken), then you *will* have the tx
So on a good system the delay should be really small (especially if you
compare to what it takes to transmit the whole packet to the other end). On a
bad system where the delay can be long, then you will need the fix anyway.
some kind of heuristic to this - eg switch to delaying if you exceed
50 failures in a 60 second period.