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Re: LTP testing (shmat01)

To: Jun Sun <jsun@mvista.com>
Subject: Re: LTP testing (shmat01)
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Mon, 8 Jul 2002 19:45:39 +0200
Cc: Carsten Langgaard <carstenl@mips.com>, linux-mips@oss.sgi.com
In-reply-to: <3D29CC6B.5090004@mvista.com>; from jsun@mvista.com on Mon, Jul 08, 2002 at 10:31:23AM -0700
References: <3D246924.542682B2@mips.com> <20020704193414.A29570@dea.linux-mips.net> <3D249181.D9147AAE@mips.com> <20020704215614.B29422@dea.linux-mips.net> <3D29CC6B.5090004@mvista.com>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5.1i
On Mon, Jul 08, 2002 at 10:31:23AM -0700, Jun Sun wrote:

> I think this is also an effective way to avoid cache aliasing.

Correct.  At the same time the choice of this value also tends to cause
bad use of L2 caches ...

> As long as your cache size is less than 256K, you don't get cache aliasing
> through shared memory.

Actually the "alias set" has to be less than 256kB.  On existing MIPS
implementations it's at most 16kB; a sillyness of the R4000 / R4400 VCE
exceptions makes a value of 32kB mandatory for poerformance reasons.

> Perhaps other arches don't have cache aliasing?  I know for sure i386 
> does not have that effect.

The problem doesn't exist on physically indexed caches.  Also on read-only
caches such as the instruction cache it usually can be ignored.  So for
example the R2000, R3000, SB1 cores, RM7000, R4kc and R5kc in the right
configurations and the R10000 family don't suffer from aliases.  Details
are messy :)

  Ralf


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