On Wed, 27 Mar 2002, Harald Koerfgen wrote:
> The 7990 is basically a 16-bit chip in a 32-bit environment, and, AFAIR, uses
> two different DMA modes to access host memory. One is a 16-bit word-by-word
> access for the ring descriptors and the other is 8 16-bit-words-bursts for
> accessing the ring buffers themselves, where the LANCE only generates one
> target address per burst.
>
> The IOASIC is, just as the CPU, only capable of doing 32-bit transfers
> to/from memory. So 16-bit LANCE accesses are translated into 32-bit IOASIC
> accesses but a part of the DMA target addresses are generated by the LANCE.
But the I/O ASIC chip is smart enough to merge data from the 8-bit ROM
device without problems and present four consecutive bytes as 32-bit
quantities to the host CPU. Why couldn't it do the same for the LANCE?
Host memory addresses are generated on behalf of the LANCE by the I/O ASIC
anyway.
Of course not all designers have a clue, sigh... A brief study of
available documentation suggests no merging mode was implemented for the
LANCE and bit 0 of addresses generated is simply hardwired to 0. :-(
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
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