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Re: pci config cycles on VRC-5477

To: Gerald Champagne <gerald.champagne@esstech.com>
Subject: Re: pci config cycles on VRC-5477
From: Jun Sun <jsun@mvista.com>
Date: Mon, 11 Mar 2002 14:24:09 -0800
Cc: linux-mips@oss.sgi.com
References: <3C8D26C8.2060903@esstech.com>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:0.9.4) Gecko/20011126 Netscape6/6.2.1
Gerald Champagne wrote:


I'm studying the VRC-5477 code and I'm trying to understand how pci config
cycles can work reliably with the current code.  It looks like the pci
config code must execute with interrupts disabled, but I can't find code
that disables interrupts.  Can someone offer a few pointers?  Here's why
I ask...

All pci io, memory, and config accesses on the 5477 are performed through
two windows in the cpu address space. Normally these two windows are configured
to perform pci memory and io accesses, and any driver can access pci io and
memory at any time. In order to perform a pci config access, one of the two
windows must be remapped to perform pci config cycles.  The code in
read_config_dword() looks something like this:

- Call ddb_access_config_base() to reconfigure the window into pci memory space
  to access pci config space instead.

- Read from pci config space by reading from an offset into the window.

- Call ddb_close_config_base to restore the registers to the original values.

It looks like anything can interrupt this an try to perform a pci memory
access while the window is programmed to perfom config cycles.

Did I miss something, or is this a bug?



Your understanding is correct.  I think this is a bug.

Do you actually see the bug happening? So far it has never hit me, but maybe due to the drivers that are loaded on my configuration.

Jun


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