On Wed, 27 Feb 2002, Kevin Paul Herbert wrote:
> What is the intention of CONFIG_CPU_HAS_WB? On an RM7000, am I better
> off doing a pipeline flush (the nops in wbflush.h) or a sync
> instruction? Also, any guidance on whether I should go out and ensure
> writes have completed in PCI host adapters and bridges, or whether
> this is excessive paranoia.
The conclusion seems to have been that CPU_HAS_WB is only for a particular
kind of WB that did not maintain PCI-type ordering rules on uncached
accesses. RM7K assures ordering of uncached reads/writes and does not
return read data from the WB so the WB is transparent.
The MB fixup patch that Maciej has seems to clean up most of the rest of
the issues with WB's and MB's by using sync in the proper places.
Linux has no primitives that assure memory operations have been flushed
through the entire PCI bus tree (there is no PCI op that will do this)..