| To: | Andre.Messerschmidt@infineon.com |
|---|---|
| Subject: | Re: Wait instruction on 5kc |
| From: | Carsten Langgaard <carstenl@mips.com> |
| Date: | Wed, 27 Feb 2002 19:24:52 +0100 |
| Cc: | linux-mips@oss.sgi.com |
| Organization: | MIPS Technologies |
| References: | <86048F07C015D311864100902760F1DD01B5E73C@dlfw003a.dus.infineon.com> |
| Sender: | owner-linux-mips@oss.sgi.com |
Andre.Messerschmidt@infineon.com wrote: > Hi. > > Is there a patch available for the wait instruction bug in the 5kc (RTL > Revision >= 2.1)? It's been fixed in RTL revision >=2.3. > > As a hack I changed it to nop (in r4k_wait() ), but I believe there is a > clever solution for this. You can remove CPU_5KC from the case statement in check_wait in the file arch/mips/kernel/setup.c > > regards > -- > Andre Messerschmidt > > Application Engineer > Infineon Technologies AG |
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