Scott A McConnell (email@example.com) writes:
> I have been trying to track down and resolve a spurious interrupt
> problem. I have attached some output and the code used to generate it in
Part of your problem may be write buffer hell.
Whatever you do to clear the interrupt when you've done with it
involves writing to the 8259 controller. It's probably a long way
away - probably through a PCI bus to a simulated ISA bus. Somewhere
along the line the writes will be 'posted'; your CPU is fast, so when
your CPU emerges from its interrupt routine the write may not have
reached the 8259 yet, and you'll get a spurious interrupt.
The code which switches off the interrupt at the 8259 should probably
be equipped with a 'barrier' call to some system function which waits
until the write has really happened.
Then 8259s are ugly things which have some very CPU-specific
interactions with x86 CPUs. In a non-x86 context you need to
initialise them in particular ways.
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