>>>>> On Thu, 21 Feb 2002 15:12:43 +0100 (MET), "Maciej W. Rozycki"
>>>>> <firstname.lastname@example.org> said:
macro> With respect to cache refills (what is already cached is
macro> irrelevant, obviously, as read accesse to it don't appear
macro> externally), "32-bit RISC Microprocessor TX39 Family Core
macro> Architecture User's Manual" seems to contradict. In the
macro> description of the "sync" instruction it states:
macro> "Interlocks the pipeline until the load, store or data cache
macro> refill operation of the previous instruction is completed. The
macro> R3900 Processor Core can continue processing instructions
macro> following a load instruction even if a cache refill is caused
macro> by the load instruction or a load is made from a noncacheable
macro> area. Executing a SYNC instruction interlocks subsequent
macro> instructions until the SYNC instruction execution is completed.
macro> This ensures that the instructions following a load instruction
macro> are executed in the proper sequence."
The contradiction is came from some confusion about usage of a word
"Core" in TX39 manual. Maybe a writer of the quoted statements
assumes a write buffer is outside of a "R3900 Processor Core". So if
he said "operation is completed" it means "data are sent to a write
buffer". Of course this point of view is not acceptable for software
macro> It's clear "sync" is strong on the TX39, stronger then required
macro> by MIPS II.
So unfortunately this is not true.