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Re: FPU emulator unsafe for SMP?

To: Ralf Baechle <ralf@oss.sgi.com>
Subject: Re: FPU emulator unsafe for SMP?
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Wed, 20 Feb 2002 16:45:08 +0100 (MET)
Cc: Jun Sun <jsun@mvista.com>, "Kevin D. Kissell" <kevink@mips.com>, linux-mips@oss.sgi.com
In-reply-to: <20020220160513.A17227@dea.linux-mips.net>
Organization: Technical University of Gdansk
Sender: owner-linux-mips@oss.sgi.com
On Wed, 20 Feb 2002, Ralf Baechle wrote:

> >  Ill???  I think someone was just longsighted enough not to limit PTEs to
> > 38-bit physical addresses.  A shift costs a single cycle if we want to
> > save memory. 
> 
> The idea of the register was to directly generate the address of a PTE.

 And it does -- doesn't it?  It simply cannot fit all needs at once.  What
about pages larger than 4kB, for example?

> An extra instruction in TLB exception handlers isn't only visible in
> performance, it also means introducing constraints on the address itself -

 The performance is an issue, of course -- you get about 10% hit in the
exception handler.  You need to decide (possibly at the run time) what's
more important: the gain from a faster TLB refill or the gain from a
compression of page tables. 

> an arithmetic shift by one bit for 4 byte PTEs will result in the two
> high bits of the address being identical, an arithmetic shift will make
> the high bit a null etc.  Just on 32-bit kernels on 64-bit hw you're
> lucky, you have a bit 32 in c0_context which will be shifted into bit 31.

 Since the address is virtual -- what's the deal?

> Messy?

 Hardly.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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