Somewhere in this thread:
> > > > > Hmm, I see. The lazy fpu context switch code is not SMP safe.
> > > > > I see fishy things like "last_task_used_math" etc...
Lazy FPU context switching? Let's turn the whole thing off...
It may be heretical... but the lazy FPU context switch was invented
for 16MHz CPUs using a write-through cache and non-burst memory, where
saving 16 x 64-bit registers took 6us or so (and quite a bit less,
later, to read them back). Call it 8us.
A 500MHz CPU with a writeback primary cache - which typically keeps up
with the CPU pipeline - takes about 120ns to do the job (there are
more registers these days). The overhead is not only less than 2% in
absolute terms, but is about a third what it used to be relative to
the overall CPU performance...
Really, is it worth all this trouble?
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