[Top] [All Lists]

Re: PATCH: Fix ll/sc for mips (take 3)

To: Hartvig Ekner <>
Subject: Re: PATCH: Fix ll/sc for mips (take 3)
From: Ralf Baechle <>
Date: Tue, 5 Feb 2002 19:59:12 +0100
Cc: "Maciej W. Rozycki" <>, Justin Carlson <>, Daniel Jacobowitz <>, "H . J . Lu" <>, Dominic Sweetman <>, GNU C Library <>,
In-reply-to: <>; from on Tue, Feb 05, 2002 at 01:38:34PM +0100
References: <> <>
User-agent: Mutt/1.2.5i
On Tue, Feb 05, 2002 at 01:38:34PM +0100, Hartvig Ekner wrote:

> Some of MIPS's cores do externalize the event of a "LL" and make it
> visible on the bus interface. Similarly, the SC is externalized and
> requires a go/nogo response from the system logic. Think of it as
> putting a shared LLAddr & LLBit outside the processor. The SC will
> only succeed if the internal LLBit is ok *and* the external logic gives
> the go-ahead as well.
> The reasoning behind all this is that one can then utilize LL/SC in
> multi CPU systems without full coherency support being required.
> But then again, this might not be relevant for MIPS/Linux as it will not
> run without full HW coherency on multiple CPUs?

Linux could easily be hacked into handle such a configuration as a cluster.
Anything else would be a pretty large job.


<Prev in Thread] Current Thread [Next in Thread>