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Re: PATCH: Fix ll/sc for mips (take 3)

To: Hartvig Ekner <hartvige@mips.com>
Subject: Re: PATCH: Fix ll/sc for mips (take 3)
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Tue, 5 Feb 2002 19:59:12 +0100
Cc: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>, Justin Carlson <justinca@ri.cmu.edu>, Daniel Jacobowitz <dan@debian.org>, "H . J . Lu" <hjl@lucon.org>, Dominic Sweetman <dom@algor.co.uk>, GNU C Library <libc-alpha@sources.redhat.com>, linux-mips@oss.sgi.com
In-reply-to: <200202051238.NAA03846@copsun18.mips.com>; from hartvige@mips.com on Tue, Feb 05, 2002 at 01:38:34PM +0100
References: <Pine.GSO.3.96.1020205131750.9674E-100000@delta.ds2.pg.gda.pl> <200202051238.NAA03846@copsun18.mips.com>
Sender: owner-linux-mips@oss.sgi.com
User-agent: Mutt/1.2.5i
On Tue, Feb 05, 2002 at 01:38:34PM +0100, Hartvig Ekner wrote:

> Some of MIPS's cores do externalize the event of a "LL" and make it
> visible on the bus interface. Similarly, the SC is externalized and
> requires a go/nogo response from the system logic. Think of it as
> putting a shared LLAddr & LLBit outside the processor. The SC will
> only succeed if the internal LLBit is ok *and* the external logic gives
> the go-ahead as well.
> 
> The reasoning behind all this is that one can then utilize LL/SC in
> multi CPU systems without full coherency support being required.
> 
> But then again, this might not be relevant for MIPS/Linux as it will not
> run without full HW coherency on multiple CPUs?

Linux could easily be hacked into handle such a configuration as a cluster.
Anything else would be a pretty large job.

  Ralf

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