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Re: PATCH: Fix ll/sc for mips (take 3)

To: macro@ds2.pg.gda.pl (Maciej W. Rozycki)
Subject: Re: PATCH: Fix ll/sc for mips (take 3)
From: Hartvig Ekner <hartvige@mips.com>
Date: Tue, 5 Feb 2002 20:28:34 +0100 (MET)
Cc: linux-mips@oss.sgi.com
In-reply-to: <Pine.GSO.3.96.1020205134113.9674G-100000@delta.ds2.pg.gda.pl> from "Maciej W. Rozycki" at Feb 05, 2002 02:28:59 PM
Sender: owner-linux-mips@oss.sgi.com
Maciej W. Rozycki writes:
>  How do you maintain coherency on such a system?  To support such a model
> all shared area write accesses should be followed by explicit
> synchronization requests.  It should be trivial but tedious to do for
> Linux, but it might not be that easy for threads.

This would have to be a loosely coupled system - something using either
software coherency or uncached accesses for the shared areas. And then
LL/SC for synchronization primitives.

There are a fair number of SOC designs like this, even with more than
two processors.

/Hartvig

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