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Re: PATCH: Fix ll/sc for mips (take 3)

To: Hartvig Ekner <hartvige@mips.com>
Subject: Re: PATCH: Fix ll/sc for mips (take 3)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Tue, 5 Feb 2002 14:28:59 +0100 (MET)
Cc: Ralf Baechle <ralf@oss.sgi.com>, Justin Carlson <justinca@ri.cmu.edu>, Daniel Jacobowitz <dan@debian.org>, "H . J . Lu" <hjl@lucon.org>, Dominic Sweetman <dom@algor.co.uk>, GNU C Library <libc-alpha@sources.redhat.com>, linux-mips@oss.sgi.com
In-reply-to: <200202051238.NAA03846@copsun18.mips.com>
Organization: Technical University of Gdansk
Sender: owner-linux-mips@oss.sgi.com
On Tue, 5 Feb 2002, Hartvig Ekner wrote:

> Some of MIPS's cores do externalize the event of a "LL" and make it
> visible on the bus interface. Similarly, the SC is externalized and
> requires a go/nogo response from the system logic. Think of it as
> putting a shared LLAddr & LLBit outside the processor. The SC will
> only succeed if the internal LLBit is ok *and* the external logic gives
> the go-ahead as well.

 OK, but an external register shouldn't need any additional CPU time to
get its contents latched. 

> The reasoning behind all this is that one can then utilize LL/SC in
> multi CPU systems without full coherency support being required.

 Nor should an external comparator.

> But then again, this might not be relevant for MIPS/Linux as it will not
> run without full HW coherency on multiple CPUs?

 How do you maintain coherency on such a system?  To support such a model
all shared area write accesses should be followed by explicit
synchronization requests.  It should be trivial but tedious to do for
Linux, but it might not be that easy for threads.

 One bit I've forgotten about "ll" -- it also implies a "sync".

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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