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Re: PATCH: Fix ll/sc for mips (take 3)

To: hjl@lucon.org
Subject: Re: PATCH: Fix ll/sc for mips (take 3)
From: Hiroyuki Machida <machida@sm.sony.co.jp>
Date: Sat, 02 Feb 2002 11:37:17 +0900 (JST)
Cc: macro@ds2.pg.gda.pl, libc-alpha@sources.redhat.com, linux-mips@oss.sgi.com
In-reply-to: <20020201151513.A15913@lucon.org>
References: <20020201102943.A11146@lucon.org> <20020201180126.A23740@nevyn.them.org> <20020201151513.A15913@lucon.org>
Sender: owner-linux-mips@oss.sgi.com
From: "H . J . Lu" <hjl@lucon.org>
Subject: Re: PATCH: Fix ll/sc for mips (take 3)
Date: Fri, 1 Feb 2002 15:15:13 -0800

> Why not? Can you show me a MIPS II or above CPU which doesn't have
> branch-likely instruction? From gcc,
> 
> /* ISA has branch likely instructions (eg. mips2).  */
> /* Disable branchlikely for tx39 until compare rewrite.  They haven't
>    been generated up to this point.  */
> #define ISA_HAS_BRANCHLIKELY    (mips_isa != 1                          \
>                                  /* || TARGET_MIPS3900 */)                    
>   
> 
> Did I miss something?

I think we can assume CPU has branch-likely insns, if CPU has MIPS
ISA 2 or greater ISA, as H.J said. I don't know any exception of
this. If anyone know exceptions, please let us know.

(FYI: we can't assume CPU has LL/SC even if CPU has branch-likely
insns. )

HL's patch looks good for me.

---
Hiroyuki Machida
Sony Corp.

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