On Wed, 2002-01-30 at 14:33, Matthew Dharm wrote:
> Damn. The entire line of processors from the RM7000 to the 7000A,
> 7000B, 7061A, and 7065A all have a bug which involves invalid TLB
> entries.
>
> I've sent the errata to Ralf only for review. Basically, under
> certain circumstances the processor will take the "TLB refill"
> exception vector instead of the "TLB invalid" vector.
What's the behavior if the invalid entry is not fixed up and we replay
the offending instruction? If there's a guarantee that it won't take
the wrong vector repeatedly, then this would be trivial to fix (and may
not need one at all for correctness).
-Justin
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