As you said, following codes can run fine if CPU has brach-likely.
From: "Kevin D. Kissell" <email@example.com>
Subject: Re: patches for test-and-set without ll/sc (Re: thread-ready ABIs)
Date: Tue, 22 Jan 2002 18:16:25 +0100
> .set noreorder
> li t0,MAGIC_COOKIE
> mov k1,t0
> lw t1,0(a0)
> addiu t1,t1,1
> BEQL k1,t0,done
> sw t1,0(a0)
> b Retry
> jr ra
> If there is any doubt about the possibility of the
> MAGIC_COOKIE value being left in k1 (or
> k0, which could also be used as the "LL flop"
> if its behavior is more easily constrained), an
> explicit operation at the end of the fault handlers
> could be used to clear the register. That would
> still be far less complex and intrusive than the mods
> that you suggest below.
I think we should always "clear" k1 at the end of exception handler.
(Above "clear" means "set !MAGIC_COOKIE"). It's conaervative way,
but robust aginst future changes in exception handler.
> It should in principle be SMP safe.
I don't think so.
THREAD A is bound to CPU A and THREAD B is bound to CPU B.
THREAD A and THREAD B are running on_atomic_inc_nollsc().
Two threads are really running at the same time, without
context-switch. In this case nobody clear k1.
Anyway, I will merge your brach-likely method and make some changes.
This change will provide signle interface of user level
test-and-set(), without LL/SC instruction emulation nor
system-call. So everyone will be able to run single user program
binary to on following three types of CPUs;
CPU has LL/SC,
CPU has no LL/SC, but has branch-likely and
CPU has neither LL/SC nor branch-likely.