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Re: Mips IRQ support

To: "TWEDE,ROGER (HP-Boise,ex1)" <roger_twede@hp.com>
Subject: Re: Mips IRQ support
From: Jun Sun <jsun@mvista.com>
Date: Tue, 22 Jan 2002 17:27:49 -0800
Cc: linux-mips@oss.sgi.com
References: <CBD6266EA291D5118144009027AA63353F92B7@xboi05.boi.hp.com>
Sender: owner-linux-mips@oss.sgi.com
"TWEDE,ROGER (HP-Boise,ex1)" wrote:
> 
> Are there any plans to provide full MIPS irq support in the general mips irq
> code?
> 
> The only machine that appears to attempt to fully support the MIPS interrupt
> set currently is the gt64120/momenco_ocelot machine.
> 
> It uses the define CP0_S1_INTCONTROL ($20) to get at the upper interrupt
> lines ( > 8 ).
> 
> Anyone else find that support for this MIPS hardware would be best placed in
> the standard irq code rather than each machine variant having to
> re-implement it itself (as the irq code was in the past).
> 

Yes.

The best way is to provide hw_irq_controller structure for the extended CPU
IRQ feature.  See arch/mips/kernel/irq_cpu.c file and its related config
option.

Jun

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